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IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
16-BIT PARALLEL CMOS MULTIPLIERS
IDT7216L
FEATURES:
* * * * * * * * * * * * 16 x 16 parallel multiplier with double precision product 16ns clocked multiply time Low power consumption: 120mA Produced with advanced submicron CMOS high performance technology IDT7216L is pin- and function compatible with TRW MPY016H/K and AMD Am29516 Configured for easy array expansion User-controlled option for transparent output register mode Round control for rounding the MSP Input and output directly TTL-compatible Three-state output Available in PLCC Speeds available: L16/20/25/35/45/55/65
DESCRIPTION:
The IDT7216 is a high-speed, low-power 16 x 16-bit multiplier, ideal for fast, real time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's high-performance, submicron CMOS technology, has achieved speeds comparable to bipolar (20ns max.), at 1/ 10 the power consumption. The IDT7216 is ideal for applications requiring high-speed multiplication such as fast Fourier transform analysis, digital filtering, graphic display systems, speech synthesis and recognition and in any system requirement where multiplication speeds of a mini/microcomputer are inadequate. All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered D-type flip-flop. In the IDT7216, there are independent clocks (CLKX, CLKY, CLKM, CLKL) associated with each of these registers. The IDT7216 offers additional flexibility with the FA control and MSPSEL functions. The FA control formats the output for two's complement by shifting the MSP up one bit and then repeating the sign bit in the MSB of the LSP. The MSPSEL low selects the MSP to be available at the product output port, while a high selects the LSP to be available. Keeping this pin low will ensure compatibility with the TRW MPY016H.
FUNCTIONAL BLOCK DIAGRAM
XM X15 0
RND
YM
Y15 -
0/P 15 16
-
0
16
XREGISTER CLKX CLKY
REGISTER
YREGISTER
OEL
MULTIPLIER ARRAY
FA
FORMAT ADJUST MSP REGISTER LSP REGISTER
FT
CLKM CLKL
16
16
MSPSEL OEP
MULTIPLEXER
PRODUCT
16
MSPOUT (P31 - P16)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2001 Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC-5746/1
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
X12 X11 NC X10 CLKY
44
X9
X8
X7
X6
X5
X4
X3
X2
X1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
X0
46
OEL
45
X13 X14 X15 CLKX RND XM YM Vcc Vcc GND GND MSPSEL FA FT OEP CLKM NC
61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9
CLKL
43 42 41 40 39 38 37
NC P0,Y0 P1,Y1 P2,Y2 P3,Y3 P4,Y4 P5,Y5 P6,Y6 P7,Y7 P8,Y8 P9,Y9 P10,Y10 P11,Y11 P12,Y12 P13,Y13 P14,Y14 P15,Y15
J68-1
36 35 34 33 32 31 30 29 28 27
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P9,P25
P8,P24
P7,P23
P6,P22
P5,P21
P4,P20
P3,P19
P15,P31
P14,P30
P13,P29
P12,P28
P11,P27
P10,P26
P2,P18
P1,P17
P0,P16
PLCC TOP VIEW
2
NC
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TA TBIAS TSTG IOUT Description Power Supply Voltage Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Max -0.5 to +7 VCC + 0.5 0 to +70 -55 to +125 -55 to +125 50 Unit V V C C C mA
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
NOTE: 1. This parameter is sampled and not 100% tested.
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name X0 - X15 Y0 - Y15/ P0 - P15 P16 - P31 OEL OEP XM, YM RND O I I I I I/O I I/O Data Inputs Y0 - Y15 are data inputs P0 - P15 are LSP register output, enabled when OEL = 0 Data Output (LSP or MSP) Output enable control for LSP (least significant product). When LOW enables P0 - P15. When HIGH P0 - P15 tristated. Output enable control for MSP (most significant product). When LOW enables P16 - P31. When HIGH P16 - P31 tristated. Mode control for each data word. LOW designates unsigned data input and HIGH designates two's complement. "Round" control for rounding of MSP. When HIGH, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When RND = 1 and FA = 0, 1 is added to the 2-16 bit (P14). The RND input is registered. It is clocked on the rising edge of the logical OR of CLKX and CLKY. Rounding always occurs in the positive direction which may introduce a systematic bias. MSPSEL FA FT CLKX CLKY CLKL CLKM I I I I I I I When LOW, MSP is output on P16 - P31 lines. When HIGH, LSP is output on P16 - P31. Format adjust control. When HIGH, a full 32 bit product is selected. When LOW, a left shifted 31 bit product is selected with the sign bit replicated in the LSP. FA is normally HIGH, except for certain fractional two's complement applications (see multiplier input / output formats). Flow through control. When HIGH, both MSP and LSP registers are by-passed. X register clock input. Also clocks RND register. Y register clock input. Also clocks RND register. LSP register clock input. MSP register clock input. Description
3
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 10%
Symbol VIH VIL ILI ILO ICC ICCQ1 ICCQ2 ICC/f(2,3) VOH VOL(4) IOS Parameter Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Power Supply Current Quiescent Power Supply Current Quiescent Power Supply Current Increase in Power Supply Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 0 to VCC VCC = Max., OE = 2V, VOUT = 0 to VCC VCC = Max., Outputs Disabled, f = 10MHz(2) VIN VIH, VIN VIL VIN VCC - 0.2V, VIN 0.2V VCC = Max., Outputs Disabled VCC = Min., IOH = -2mA VCC = Min., IOL = 8mA VCC = Max., VO = GND Min. 2 -- -- -- -- -- -- -- 2.4 -- -20 Typ.(1) -- -- -- -- 40 20 4 -- -- -- -- Max. -- 0.8 10 10 80 40 20 4 -- 0.4 -120 Unit V V A A mA mA mA mA/MHz V V mA
NOTES: 1. Typical implies VCC = 5V and TA = +25C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 80+ 4(f -10)mA; for the military range, ICC = 100 + 6(f -10). f = operating frequency in MHz and f = 1/tMC. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMC >65ns.
4
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 10%
7216L16 Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tHCL Parameter Unclocked Multiply Time(4) Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width HIGH Clock Pulse Width LOW MSPSEL to Product Out(4) Output Clock to P(4) Output Clock to Y(4) 3-State Enable Time 3-State Disable Time(2) Clock LOW Hold Time CLKXY Relative to CLKML (1,3) Min. 2 2 10 1 7 7 2 2 2 -- -- 0 Max. 25 16 -- -- -- -- 15 15 15 15 15 -- 2 2 11 1 9 9 2 2 2 -- -- 0 7216L20 Min. Max. 30 20 -- -- -- -- 18 18 18 18 18 -- 7216L25 Min. 2 2 12 2 10 10 2 2 2 -- -- 0 Max. 38 25 -- -- -- -- 20 20 20 20 20 -- 7216L35 Min. 2 2 12 3 10 10 2 2 2 -- -- 0 Max. 55 35 -- -- -- -- 25 25 25 25 22 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
7216L45 Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tHCL Parameter Unclocked Multiply Time(4) Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width HIGH Clock Pulse Width LOW MSPSEL to Product Out(4) Output Clock to P(4) Output Clock to Y(4) 3-State Enable Time 3-State Disable Time(2) Clock LOW Hold Time CLKXY Relative to CLKML (1,3) Min. 2 2 15 3 15 15 2 2 2 -- -- 0 Max. 65 45 -- -- -- -- 25 25 25 25 22 --
7216L55 Min. 2 2 20 3 15 20 2 2 2 -- -- 0 Max. 75 55 -- -- -- -- 25 30 30 30 25 --
7216L65 Min. 2 2 20 3 15 20 2 2 2 -- -- 0 Max. 85 65 -- -- -- -- 30 30 30 35 25 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured 500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested.
5
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
TIMING DIAGRAM
tPWH CLKX CLKY tS INPUT X1, Y1 RND tMC CLKM CLKL tPDY OUTPUT Y tH tPWL tHCL
CLKM CLKL tPDSEL MSPSEL tPDP OUTPUT P tMUC
6
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
BINARY POINT
X15 X14 -2 0 2
-1
X13 2
-2
X12 2
-3
X11 2
-4
X10 2
-5
X9 2
-6
X8 2
-7
X7 2
-8
X6 2
-9
X5 2
-10
X4 2
-11
X3 2
-12
X2 2
-13
X1 2
-14
X0 2
-15
SIGNAL DIGITAL VALUE
Y15 Y14 X -2 0 2
-1
Y13 2
-2
Y12 2
-3
Y11 2
-4
Y10 2
-5
Y9 2
-6
Y8 2
-7
Y7 2
-8
Y6 2
-9
Y5 2
-10
Y4 2
-11
Y3 2
-12
Y2 2
-13
Y1 2
-14
Y0 2
-15
SIGNAL DIGITAL VALUE
P31
*=
P30 2
-1
P29 2
-2
P28 2
-3
P27 2
-4
P26 2
-5
P25 2
-6
P24 2
-7
P23 2
-8
P22 2
-9
P21 2
-10
P20 2
-11
P19 2
-12
P18 2
-13
P17 2
-14
P16 P15 2
-15
P14 2
-16
P13 2
-17
P12 2
-18
P11 2
-19
P10 2
-20
P9 2
-21
P8 2
-22
P7 2
-23
P6 2
-24
P5 2
-25
P4 2
-26
P3 2
-27
P2 2
-28
P1 2
-29
P0 2
-30
SIGNAL
FA = 0
-2 0
2
0
DIGITAL VALUE
MSP
LSP
P31 P30
=
P29 2
-1
P28 2
-2
P27 2
-3
P26 2
-4
P25 2
-5
P24 2
-6
P23 2
-7
P22 2
-8
P21 2
-9
P20 2
-10
P19 2
-11
P18 2
-12
P17 2
-13
P16 2
-14
P15 2
-15
P14 2
-16
P13 2
-17
P12 2
-18
P11 2
-19
P10 2
-20
P9 2
-21
P8 2
-22
P7 2
-23
P6 2
-24
P5 2
-25
P4 2
-26
P3 2
-27
P2 2
-28
P1 2
-29
P0 2
-30
SIGNAL
FA = 1
-2 1
2
0
DIGITAL VALUE
MSP
LSP
7
BINARY POINT X15 X14 -2 0 2
-1
Fractional Two's Complement Notation
X13 2
-2
X12 2
-3
X11 2
-4
X10 2
-5
X9 2
-6
X8 2
-7
X7 2
-8
X6 2
-9
X5 2
-10
X4 2
-11
X3 2
-12
X2 2
-13
X1 2
-14
X0 2
-15
SIGNAL DIGITAL VALUE
COMMERCIAL TEMPERATURE RANGE
Y15 Y14 X 2
-1
Y13 2
-3
Y12 2
-4
Y11 2
-5
Y10 2
-6
Y9 2
-7
Y8 2
-8
Y7 2
-9
Y6 2
-10
Y5 2
-11
Y4 2
-12
Y3 2
-13
Y2 2
-14
Y1 2
-15
Y0 2
-16
SIGNAL DIGITAL VALUE
2
-2
P31
=
P30 2
-2
P29 2
-3
P28 2
-4
P27 2
-5
P26 2
-6
P25 2
-7
P24 2
-8
P23 2
-9
P22 2
-10
P21 2
-11
P20 2
-12
P19 2
-13
P18 2
-14
P17 2
-15
P16 2
-16
P15 2
-17
P14 2
-18
P13 2
-19
P12 2
-20
P11 2
-21
P10 2
-22
P9 2
-23
P8 2
-24
P7 2
-25
P6 2
-26
P5 2
-27
P4 2
-28
P3 2
-29
P2 2
-30
P1 2
-31
P0 2
-32
SIGNAL DIGITAL VALUE
FA = 1
2
-1
MSP
LSP
MANDATORY
Fractional Unsigned Magnitude Notation
* In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000...0 with 1,000.0 yeilding an erroneous product of -1 in the fraction case and -230 in the integer case.
BINARY POINT
X15 X14 X2 2
-13
X13 X0 2
-15 -6
X12 2
-7
X11 2
-8
X10 X8 2
-9
X9 2
-10
X7 2
-11
X6 2
-12
X5 2
-14
X4 SIGNAL (TWO'S COMPONENT) DIGITAL VALUE
X3
X1
-2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
Y15 Y14 Y2 2
-14
Y13 Y0 2
-16 -6
Y12 2
-7
Y11 2
-8
Y10 2
-9
Y9 2
-10
Y8 2
-11
Y7 2
-12
Y6 2
-13
Y5 2
-15
Y4 SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE
Y3
Y1
X
2
-1
2
-2
2
-3
2
-4
2
-5
2
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
P31 P15 2 LSP
-16
P30 P14 2
-17
P29 P13 2
-18
P28 P12 2
-19
P27 P11 2
-20
P26 P10 2
-21
P25 P9 2
-22
P24 P8 2
-23
P23 P7 2
-24
P22 P6 2
-25
P21 P5 2
-26
P20 P4 2
-27
P19 2
-12
P18 2
-13
P17 2
-14
P16 2
-15
P3 2
-28
P2 2
-29
P1 2
-30
P0 2
-31
SIGNAL DIGITAL VALUE
FA = 1
=
-6
-2 MSP
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
2
-7
2
-8
2
-9
2
-10
2
-11
MANDATORY
Fractional Mixed Mode Notation
BINARY POINT
8
X15 X14 -2
15
X13 2
13
X12 2
12
X11 2
11
X10 2
10
X9 2
9
X8 2
8
X7 2
7
X6 2
6
X5 2
5
X4 2
4
X3 2
3
X2 2
2
X1 2
1
X0 2
0
SIGNAL DIGITAL VALUE
2
14
Y15 Y14 X -2
15
Y13 2
13
Y12 2
12
Y11 2
11
Y10 2
10
Y9 2
9
Y8 2
8
Y7 2
7
Y6 2
6
Y5 2
5
Y4 2
4
Y3 2
3
Y2 2
2
Y1 2
1
Y0 2
0
SIGNAL DIGITAL VALUE
2
14
P31 2 MSP P24 2 MSP
24 23
P30 2
22
P29 2
21
P28 2
20
P27 2
19
P26 2
18
P25 2
17
P24 2
16
P23 2
15
P22 2
-30
P21 2
P20
P19
P18
P17
P16 P15
P14
14
P13 2
13
P12 2
12
P11 2
11
P10 2
10
P9 2
9
P8 2
8
P7 2 LSP
7
P6 2
6
P5 2
5
P4 2
4
P3 2
3
P2 2
2
P1 2
1
P0 2
0
SIGNAL
FA = 0
*=
-2
30
2
29
2
28
2
27
2
26
2
25
2
24
DIGITAL VALUE
P31 2
23
P30 2
22
P29 2
21
P28 2
20
P27 2
19
P26 2
18
P25 2
P23
P22
P21
P20
P19
P18
P17
17
P16 2
16
P15 2
15
P14 2
14
P13 2
13
P12 2
12
P11 2
11
P10 2
10
P9 2
9
P8 2
8
P7 2 LSP
7
P6 2
6
P5 2
5
P4 2
4
P3 2
3
P2 2
2
P1 2
1
P0 2
0
SIGNAL
FA = 1
=
-2
31
2
30
2
29
2
28
2
27
2
26
2
25
DIGITAL VALUE
Integer Two's Complement Notation
COMMERCIAL TEMPERATURE RANGE
* In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000...0 with 1,000.0 yeilding an erroneous product of -1 in the fraction case and -230 in the integer case.
BINARY POINT
X15 X14 X2 SIGNAL DIGITAL VALUE 2
2
X13 X0 2
0
X12 2
12
X11 2
11
X10 2
10
X9 2
9
X8 2
8
X7 2
7
X6 2
6
X5 2
5
X4 2
4
X3 2
3
X1 2
1
2
15
2
14
2
13
Y15 Y14 Y10 Y2 2
2
Y13 Y0 2
0
Y12 2
12
Y11 2
11
Y9 2
9
Y8 2
8
Y7 2
7
Y6 2
6
Y5 2
5
Y4 2
4
Y3 2
3
Y1 2
1
X 2
15
SIGNAL DIGITAL VALUE
2
14
2
13
2
10
SIGNAL P24 2 MSP LSP
24
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
P31 2
23
P30 2
22
P29 2
21
P28 2
20
P27 2
19
P26 2
18
P25 2
17
P23 2
16
P22 2
15
P21 2
14
P20 2
13
P19 2
12
P18 2
11
P17 2
10
P16 2
9
P15 2
8
P14 2
7
P13 2
6
P12 2
5
P11 2
4
P10 2
3
P9 2
P8
P7
P6
P5
P4
P3
P2
2
P1 2
1
P0 DIGITAL VALUE 2
0
2 31
2
30
2
29
2
28
2
27
2
26
2
25
FA = 1
MANDATORY
Integer Unsigned Magnitude Notation
9
BINARY POINT X15 X14 -2
15
X13 2
13
X12 2
12
X11 2
11
X10 2
10
X9 2
9
X8 2
8
X7 2
7
X6 2
6
X5 2
5
X4 2
4
X3 2
3
X2 2
2
X1 2
1
X0 2
0
2
14
SIGNAL (TWO'S COMPLEMENT) DIGITAL VALUE
Y15 Y14 X 2
15
Y13
14
Y12 2
13
Y11 2
12
Y10 2
11
Y9 2
10
Y8 2
9
Y7 2
8
Y6 2
7
Y5 2
6
Y4 2
5
Y3 2
4
Y2 2
3
Y1 2
2
Y0 2
1
2
2
0
SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE
SIGNAL P23 2
23
P31 2
22
P30 2
21
P29 2
20
P28 2
19
P27 2
18
P26 2
P25
P24
P22
P21
P20
P19
P18
P17
17
P16 2
16
P15 2
15
P14 2
14
P13 2
13
P12 2
12
P11 2
11
P10 2
10
P9 2
9
P8 2
8
P7 2 LSP
7
P6 2
6
P5 2
5
P4 2
4
P3 2
3
P2 2
2
P1 2
1
P0 DIGITAL VALUE 2
0
-2 31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
FA = 1
MSP
MANDATORY
COMMERCIAL TEMPERATURE RANGE
Integer Mixed Mode Notation
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator RT D.U.T. 50pF 500 C
L
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 3ns 1.5V 1.5V See Figure 1
V OU T
AC Test Circuit
SWITCH POSITION
Test Disable Low Enable Low All Other Tests Switch Closed Open
ESD Protection IIH INPUTS IIL R
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
VCC
IOH
Input Interface Circuit
OUTPUTS IOL
Output Interface Circuit
10
IDT7216L 16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package
J 16 20 25 35 45 55 65
Plastic Leaded Chip Carrier (J68-1)
Commercial (tMC)
L 7216
Low Power 16 x 16 M ultiplier
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
11

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